Rambus targets AI memory bottlenecks with new HBM4E controller IP

The new HBM4E Controller builds on Rambus’s track record of more than 100 HBM design wins and the company’s long-standing focus on memory interface IP. The new controller incorporates advanced ...
Semiconductor Engineering

Setting The Memory Controller Free From Managing DRAM Maintenance Ops (ETH Zurich)

A new technical paper titled “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations” was published by ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
Semiconductor Engineering

Redefining XPU Memory For AI Data Centers Through Custom HBM4: Part 3

This is the third and final of a series from Alphawave Semi on HBM4 and gives and examines custom HBM implementations. Click here for part 1, which gives an overview of the HBM standard, and here for ...
CNET

Why Intel doesn't include a memory controller on its chips

Michael Kanellos is editor at large at CNET News.com, where he covers hardware, research and development, start-ups and the tech industry overseas. If you want to know why Intel doesn't include a ...
Digi Times

Yangtze Memory partners with controller IC suppliers to promote 232-layer NAND SSD

Yangtze Memory Technologies (YMTC) is collaborating with local Chinese flash device controller suppliers to market SSDs with its 232-layer NAND chips at relatively low prices, according to sources at ...