EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Semiconductor Engineering

Better ATPG To Minimize Chip Test Time And Cost

As chips get ever bigger and more complex, the electronic design automation (EDA) industry must innovate constantly to keep up. Engineers expect every new generation of silicon to be modeled, ...
Electronic Design

What’s The Difference Between Scan ATPG And IJTAG Pattern Retargeting?

Both scan automated test pattern generation (ATPG) patterns and IJTAG patterns 1,2,3 are created for a piece of logic that is part of a much larger design. For both, the patterns are independent from ...
EDN

Product How To: DFT strategy for ARM processor-based designs

One of the most significant design trends of the decade is the widespread use of ARM® multicore processors in systems-on-chip (SoCs). Designers’ ability to easily and cost-effectively employ multiple, ...
Semiconductor Engineering

Are You Using Structural Patterns In An SLT Environment?

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and ...