There is considerable ongoing discussion on how to contain exponentially increasing test costs for systems-on-chip (SoCs) and microprocessors. As the transistor geometry shrinks and more transistors ...
Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each ...
Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory ...
Increased device complexity can be addressed by providing parallel test while decreasing the throughput overhead of the ATE architecture. The consumer world is converging, and the lines between ...
SAN FRANCISCO — During the Semicon West trade show, Agilent, Credence and Electroglas separately rolled out automatic test equipment (ATE) solutions to attack chip-testing costs. Electroglas Inc.
SAN FRANCISCO, Jan. 21, 2026 /PRNewswire/ -- PI (Physik Instrumente) announced a new technology platform for electro-optical wafer-level testing designed to validate electrical and optical device ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results