Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...

This fellow has a Hong Kong patent on eliminating dead-time-jitter. Well, I am not a PLL expert but I am pretty sure that a good PLL with a filter that works right should not really hunt around too ...

The phase locked loop, or PLL, is a real workhorse of circuit design. It is a classic feedback loop where the phase of an oscillator is locked to the phase of a ...

Some brief theory and typical measurements of phase noise. Standard analysis of PLL phase noise used by most CAD applications. How to produce the lowest phase noise at a PLL output. A standard design ...

Radiation-hardened phase-locked loop (PLL) circuits represent a critical advancement in safeguarding electronic systems against the deleterious effects of ionising radiation. These circuits are ...

For an IC building block that came into being at about the same time as the microprocessor in the late 1960s and early 1970s, the “lowly” phase-locked loop has not done too badly. The hidden beauty of ...

That big grandfather clock in the library might be an impressive piece of mechanical ingenuity, and an even better example of fine cabinetry, but we’d expect that the accuracy of a pendulum timepiece ...

LOS ALTOS, Calif.--(BUSINESS WIRE)--June 8, 2004-- True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics ...

The total power consumption of the proposed PLL is only 8.89 mW from a 1 V supply, which leads to a figure of merit of reference of -247.4 dB. Credit must be given to the creator. Only noncommercial ...