Santa Cruz, Calif. – Claiming the first hybrid approach to transistor-level timing and crosstalk analysis, Nassda Corp. this week will introduce Hanex, a product that combines static and dynamic ...
WCET analysis is essential for proving multicore real-time systems meet safety-critical deadlines under all operating ...
Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
At one time a relatively infrequent occurrence, voltage drop is now a major impediment to reliability at advanced nodes. Decades ago, voltage drop was only an issue for very large and high-speed ...
IR-drop has always been somewhat of an issue in chip design; voltage decreases as current travels along any path with any resistance. Ohm’s Law is likely the first thing that every electrical engineer ...
Nanometer design will require new thinking in timing closure. Historically, design teams relied on static timing analysis, which depends on the abstracted behavior of individual gates to perform ...
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